1. Field of the Invention
The present invention relates to a system comprising a host, a target and connection means therebetween. In particular, but not exclusively, one of the host and target may be an integrated circuit and the other of the host and target may be external to the integrated circuit.
2. Description of the Related Art
Reference is made to FIG. 1 which shows a host 2 and a target 4. The host 2 sends data to the target 4 via a connection line 6. Likewise, the target sends data to the host via a connection line 8. The target comprises a test access port (TAP) controller on an integrated circuit and the host is an off-chip counterpart to the TAP controller. One problem is that a significant length of cable, for example of the order of 0.5 meters may be provided between the host and the target. In addition, the connection between the host and the target may include signal conditioning logic such as buffers, line drivers, signal voltage level converters or the like. This means that this signal conditioning logic adds a path delay for each signal transition both for signals from the host 2 to the target 4 and from the target 4 to the host 2.
Reference is now made to FIGS. 2 and 3 which illustrate in more detail the problems which can be caused by this delay. The host 2 has a first flip flop 10. This flip flop 10 receives two inputs 12 and 14. The first input 12 is a test data input TDI and comprises the data which is to be transmitted to the target 4. The second input 14 is a clock signal TCK which controls the clocking out of the test data TDI. The clock signal TCK is also transmitted to the target 4 via a separate connection or transmission path 5.
At the target 4, there is a flip flop 16 which receives the received test data TDI′ from the host 2 at one input 18 and the received clock signal TCK′ at a second input 20. The received test data TDI′ is the same as the test data transmitted by the host 2 but with a delay resulting from the transmission of the data across the transmission path 6. The received clock signal TCK′ is likewise the same as the clock signal TCK transmitted by the host 2 but with a delay resulting form the transmission of the clock signal across the transmission path 5. The received test data TDI′ is thus clocked in using the received clock signal TCK′.
The received clock signal TCK′ provides an input 22 to a second flip flop 24. The received clock signal TCK′ is first passed through an inverter 23. A second input to the flip flop 24 is provided by a test data output TDO signal which comprises the data which is to be transmitted to the host. Accordingly, the received clock signal TCK′ in the form of its inverse, at the target 4, is also used to clock the data out to the host 2.
The host has a second flip flop 28 which receives the test data TDO′ from the target 4 and also the clock signal TCK generated by the host 2 via input 32. The received test data TDO′ is the same as the transmitted test data TDO but with a delay resulting from the transmission of the test data across path 8. The test data TDO′ received from the target 4 is thus clocked out with the clock signal TCK generated by the host 2.
FIG. 3 shows the timing of the various signals. The first signal TCK represents the clock signal timing at the host 2. The second signal TCK′ represents the clock signal timing at the target 4, the difference in timing between the two signals being due to the delay path between the host 2 and the target 4. TDI represents the timing of the data transmitted from the host 2 whilst TDI′ represents the timing of the data received at the target 4. The test data TDI transmitted by the host 2 is clocked out by the host clock signal TCK whilst the test data TDI′ received at the target 4 is clocked in by the received clock signal TCK′. The received clock signal TCK′ at the target 4 is also used to clock out the test data TDO which is transmitted from the target 4 to the host 2. However, the problem arises at the host 2 where the data TDO′ received from the target 4 is clocked in using the original clock signal TCK. If the data TDO′ transmitted from the target 4 is captured by the original clock signal TCK close to when that data is changing, the storage element capturing the data at the host 2 may enter a meta stable condition where the output may change after a nondeterministic time. Clearly this is disadvantageous.
For a standard synchronous implementation, it is a requirement in the host that the returned data from the target be captured cleanly by the clocking signal. With the arrangement shown in FIG. 2, any transition in the data from the target 4 to the host 2 will arrive back at the host 2 at least two path delay times (i.e. caused by the cabling between the host 2 and the target 4 and the target 4 and the host 2) after the significant clock transition of the clock. These two path delays are also known as the loop delay. In order to address this problem, the clocking frequency of the clock signal has been limited to the inverse of the loop delay. In some implementations, depending on which and how many clock edges are used in a clock cycle, this could lead to a maximum clock frequency of half of the inverse of the loop delay.
Accordingly, it can be appreciated that there is a need for an improved system and method for connecting a host and a target system.